Defines |
| #define | MIOS32_SPI0_PTR LPC_SSP0 |
| #define | MIOS32_SPI0_RCLK1_INIT { MIOS32_SYS_LPC_PINSEL(1, 21, 0); MIOS32_SYS_LPC_PINDIR(1, 21, 1); } |
| #define | MIOS32_SPI0_RCLK1_SET(v) { MIOS32_SYS_LPC_PINSET(1, 21, v); } |
| #define | MIOS32_SPI0_RCLK2_INIT { MIOS32_SYS_LPC_PINSEL(1, 22, 0); MIOS32_SYS_LPC_PINDIR(1, 22, 1); } |
| #define | MIOS32_SPI0_RCLK2_SET(v) { MIOS32_SYS_LPC_PINSET(1, 22, v); } |
| #define | MIOS32_SPI0_SCLK_INIT { MIOS32_SYS_LPC_PINSEL(1, 20, 3); } |
| #define | MIOS32_SPI0_MISO_INIT { MIOS32_SYS_LPC_PINSEL(1, 23, 3); } |
| #define | MIOS32_SPI0_MOSI_INIT { MIOS32_SYS_LPC_PINSEL(1, 24, 3); } |
| #define | MIOS32_SPI0_PP_INIT { LPC_PINCON->PINMODE_OD1 &= ~((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) | (1 << 20)); } |
| #define | MIOS32_SPI0_OD_INIT { LPC_PINCON->PINMODE_OD1 |= ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) | (1 << 20)); } |
| #define | MIOS32_SPI0_IN_INIT |
| #define | MIOS32_SPI0_DMA_TX_REQ 0 |
| #define | MIOS32_SPI0_DMA_RX_REQ 1 |
| #define | MIOS32_SPI0_DMA_TX_CHN 0 |
| #define | MIOS32_SPI0_DMA_RX_CHN 1 |
| #define | MIOS32_SPI1_PTR LPC_SSP1 |
| #define | MIOS32_SPI1_RCLK1_INIT { MIOS32_SYS_LPC_PINSEL(0, 6, 0); MIOS32_SYS_LPC_PINDIR(0, 6, 1); } |
| #define | MIOS32_SPI1_RCLK1_SET(v) { MIOS32_SYS_LPC_PINSET(0, 6, v); } |
| #define | MIOS32_SPI1_RCLK2_INIT { MIOS32_SYS_LPC_PINSEL(3, 26, 0); MIOS32_SYS_LPC_PINDIR(3, 26, 1); } |
| #define | MIOS32_SPI1_RCLK2_SET(v) { MIOS32_SYS_LPC_PINSET(3, 26, v); } |
| #define | MIOS32_SPI1_SCLK_INIT { MIOS32_SYS_LPC_PINSEL(0, 7, 2); } |
| #define | MIOS32_SPI1_MISO_INIT { MIOS32_SYS_LPC_PINSEL(0, 8, 2); } |
| #define | MIOS32_SPI1_MOSI_INIT { MIOS32_SYS_LPC_PINSEL(0, 9, 2); } |
| #define | MIOS32_SPI1_PP_INIT { LPC_PINCON->PINMODE_OD0 &= ~((1 << 9) | (1 << 8) | (1 << 7) | (1 << 6)); LPC_PINCON->PINMODE_OD3 &= ~((1 << 26)); } |
| #define | MIOS32_SPI1_OD_INIT { LPC_PINCON->PINMODE_OD0 |= ((1 << 9) | (1 << 8) | (1 << 7) | (1 << 6)); LPC_PINCON->PINMODE_OD3 |= ((1 << 26)); } |
| #define | MIOS32_SPI1_IN_INIT |
| #define | MIOS32_SPI1_DMA_TX_REQ 2 |
| #define | MIOS32_SPI1_DMA_RX_REQ 3 |
| #define | MIOS32_SPI1_DMA_TX_CHN 2 |
| #define | MIOS32_SPI1_DMA_RX_CHN 3 |
| #define | MIOS32_SPI2_PTR LPC_SPI |
| #define | MIOS32_SPI2_RCLK1_INIT { MIOS32_SYS_LPC_PINSEL(0, 16, 0); MIOS32_SYS_LPC_PINDIR(0, 16, 1); } |
| #define | MIOS32_SPI2_RCLK1_SET(v) { MIOS32_SYS_LPC_PINSET(0, 16, v); } |
| #define | MIOS32_SPI2_RCLK2_INIT { MIOS32_SYS_LPC_PINSEL(0, 21, 0); MIOS32_SYS_LPC_PINDIR(0, 21, 1); } |
| #define | MIOS32_SPI2_RCLK2_SET(v) { MIOS32_SYS_LPC_PINSET(0, 21, v); } |
| #define | MIOS32_SPI2_SCLK_INIT { MIOS32_SYS_LPC_PINSEL(0, 15, 3); } |
| #define | MIOS32_SPI2_MISO_INIT { MIOS32_SYS_LPC_PINSEL(0, 17, 3); } |
| #define | MIOS32_SPI2_MOSI_INIT { MIOS32_SYS_LPC_PINSEL(0, 18, 3); } |
| #define | MIOS32_SPI2_PP_INIT { LPC_PINCON->PINMODE_OD0 &= ~((1 << 21) | (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15)); } |
| #define | MIOS32_SPI2_OD_INIT { LPC_PINCON->PINMODE_OD0 |= ((1 << 21) | (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15)); } |
| #define | MIOS32_SPI2_IN_INIT |
Functions |
| s32 | MIOS32_SPI_Init (u32 mode) |
| s32 | MIOS32_SPI_IO_Init (u8 spi, mios32_spi_pin_driver_t spi_pin_driver) |
| s32 | MIOS32_SPI_TransferModeInit (u8 spi, mios32_spi_mode_t spi_mode, mios32_spi_prescaler_t spi_prescaler) |
| s32 | MIOS32_SPI_RC_PinSet (u8 spi, u8 rc_pin, u8 pin_value) |
| s32 | MIOS32_SPI_TransferByte (u8 spi, u8 b) |
| s32 | MIOS32_SPI_TransferBlock (u8 spi, u8 *send_buffer, u8 *receive_buffer, u16 len, void *callback) |
