Defines |
| #define | MIOS32_SPI0_PTR SPI1 |
| #define | MIOS32_SPI0_DMA_RX_PTR DMA2_Stream2 |
| #define | MIOS32_SPI0_DMA_RX_CHN DMA_Channel_3 |
| #define | MIOS32_SPI0_DMA_RX_IRQ_FLAGS (DMA_FLAG_TCIF2 | DMA_FLAG_TEIF2 | DMA_FLAG_HTIF2 | DMA_FLAG_FEIF2) |
| #define | MIOS32_SPI0_DMA_TX_PTR DMA2_Stream3 |
| #define | MIOS32_SPI0_DMA_TX_CHN DMA_Channel_3 |
| #define | MIOS32_SPI0_DMA_TX_IRQ_FLAGS (DMA_FLAG_TCIF3 | DMA_FLAG_TEIF3 | DMA_FLAG_HTIF3 | DMA_FLAG_FEIF3) |
| #define | MIOS32_SPI0_DMA_IRQ_CHANNEL DMA2_Stream2_IRQn |
| #define | MIOS32_SPI0_DMA_IRQHANDLER_FUNC void DMA2_Stream2_IRQHandler(void) |
| #define | MIOS32_SPI0_RCLK1_PORT GPIOB |
| #define | MIOS32_SPI0_RCLK1_PIN GPIO_Pin_2 |
| #define | MIOS32_SPI0_RCLK1_AF { } |
| #define | MIOS32_SPI0_RCLK2_PORT GPIOD |
| #define | MIOS32_SPI0_RCLK2_PIN GPIO_Pin_11 |
| #define | MIOS32_SPI0_RCLK2_AF { } |
| #define | MIOS32_SPI0_SCLK_PORT GPIOA |
| #define | MIOS32_SPI0_SCLK_PIN GPIO_Pin_5 |
| #define | MIOS32_SPI0_SCLK_AF { GPIO_PinAFConfig(GPIOA, GPIO_PinSource5, GPIO_AF_SPI1); } |
| #define | MIOS32_SPI0_MISO_PORT GPIOA |
| #define | MIOS32_SPI0_MISO_PIN GPIO_Pin_6 |
| #define | MIOS32_SPI0_MISO_AF { GPIO_PinAFConfig(GPIOA, GPIO_PinSource6, GPIO_AF_SPI1); } |
| #define | MIOS32_SPI0_MOSI_PORT GPIOA |
| #define | MIOS32_SPI0_MOSI_PIN GPIO_Pin_7 |
| #define | MIOS32_SPI0_MOSI_AF { GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_SPI1); } |
| #define | MIOS32_SPI1_PTR SPI2 |
| #define | MIOS32_SPI1_DMA_RX_PTR DMA1_Stream3 |
| #define | MIOS32_SPI1_DMA_RX_CHN DMA_Channel_0 |
| #define | MIOS32_SPI1_DMA_RX_IRQ_FLAGS (DMA_FLAG_TCIF3 | DMA_FLAG_TEIF3 | DMA_FLAG_HTIF3 | DMA_FLAG_FEIF3) |
| #define | MIOS32_SPI1_DMA_TX_PTR DMA1_Stream4 |
| #define | MIOS32_SPI1_DMA_TX_CHN DMA_Channel_0 |
| #define | MIOS32_SPI1_DMA_TX_IRQ_FLAGS (DMA_FLAG_TCIF4 | DMA_FLAG_TEIF4 | DMA_FLAG_HTIF4 | DMA_FLAG_FEIF4) |
| #define | MIOS32_SPI1_DMA_IRQ_CHANNEL DMA1_Stream3_IRQn |
| #define | MIOS32_SPI1_DMA_IRQHANDLER_FUNC void DMA1_Stream3_IRQHandler(void) |
| #define | MIOS32_SPI1_RCLK1_PORT GPIOB |
| #define | MIOS32_SPI1_RCLK1_PIN GPIO_Pin_12 |
| #define | MIOS32_SPI1_RCLK1_AF { GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_SPI2); } |
| #define | MIOS32_SPI1_RCLK2_PORT GPIOD |
| #define | MIOS32_SPI1_RCLK2_PIN GPIO_Pin_10 |
| #define | MIOS32_SPI1_RCLK2_AF { } |
| #define | MIOS32_SPI1_SCLK_PORT GPIOB |
| #define | MIOS32_SPI1_SCLK_PIN GPIO_Pin_13 |
| #define | MIOS32_SPI1_SCLK_AF { GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_SPI2); } |
| #define | MIOS32_SPI1_MISO_PORT GPIOB |
| #define | MIOS32_SPI1_MISO_PIN GPIO_Pin_14 |
| #define | MIOS32_SPI1_MISO_AF { GPIO_PinAFConfig(GPIOB, GPIO_PinSource14, GPIO_AF_SPI2); } |
| #define | MIOS32_SPI1_MOSI_PORT GPIOB |
| #define | MIOS32_SPI1_MOSI_PIN GPIO_Pin_15 |
| #define | MIOS32_SPI1_MOSI_AF { GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_SPI2); } |
| #define | MIOS32_SPI2_PTR SPI3 |
| #define | MIOS32_SPI2_DMA_RX_PTR DMA1_Stream2 |
| #define | MIOS32_SPI2_DMA_RX_CHN DMA_Channel_0 |
| #define | MIOS32_SPI2_DMA_RX_IRQ_FLAGS (DMA_FLAG_TCIF2 | DMA_FLAG_TEIF2 | DMA_FLAG_HTIF2 | DMA_FLAG_FEIF2) |
| #define | MIOS32_SPI2_DMA_TX_PTR DMA1_Stream5 |
| #define | MIOS32_SPI2_DMA_TX_CHN DMA_Channel_0 |
| #define | MIOS32_SPI2_DMA_TX_IRQ_FLAGS (DMA_FLAG_TCIF5 | DMA_FLAG_TEIF5 | DMA_FLAG_HTIF5 | DMA_FLAG_FEIF5) |
| #define | MIOS32_SPI2_DMA_IRQ_CHANNEL DMA1_Stream2_IRQn |
| #define | MIOS32_SPI2_DMA_IRQHANDLER_FUNC void DMA1_Stream2_IRQHandler(void) |
| #define | MIOS32_SPI2_RCLK1_PORT GPIOA |
| #define | MIOS32_SPI2_RCLK1_PIN GPIO_Pin_15 |
| #define | MIOS32_SPI2_RCLK1_AF { GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_SPI3); } |
| #define | MIOS32_SPI2_RCLK2_PORT GPIOB |
| #define | MIOS32_SPI2_RCLK2_PIN GPIO_Pin_8 |
| #define | MIOS32_SPI2_RCLK2_AF { } |
| #define | MIOS32_SPI2_SCLK_PORT GPIOB |
| #define | MIOS32_SPI2_SCLK_PIN GPIO_Pin_3 |
| #define | MIOS32_SPI2_SCLK_AF { GPIO_PinAFConfig(GPIOB, GPIO_PinSource3, GPIO_AF_SPI3); } |
| #define | MIOS32_SPI2_MISO_PORT GPIOB |
| #define | MIOS32_SPI2_MISO_PIN GPIO_Pin_4 |
| #define | MIOS32_SPI2_MISO_AF { GPIO_PinAFConfig(GPIOB, GPIO_PinSource4, GPIO_AF_SPI3); } |
| #define | MIOS32_SPI2_MOSI_PORT GPIOB |
| #define | MIOS32_SPI2_MOSI_PIN GPIO_Pin_5 |
| #define | MIOS32_SPI2_MOSI_AF { GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_SPI3); } |
| #define | CCR_ENABLE ((uint32_t)0x00000001) |
Functions |
| s32 | MIOS32_SPI_Init (u32 mode) |
| s32 | MIOS32_SPI_IO_Init (u8 spi, mios32_spi_pin_driver_t spi_pin_driver) |
| s32 | MIOS32_SPI_TransferModeInit (u8 spi, mios32_spi_mode_t spi_mode, mios32_spi_prescaler_t spi_prescaler) |
| s32 | MIOS32_SPI_RC_PinSet (u8 spi, u8 rc_pin, u8 pin_value) |
| s32 | MIOS32_SPI_TransferByte (u8 spi, u8 b) |
| s32 | MIOS32_SPI_TransferBlock (u8 spi, u8 *send_buffer, u8 *receive_buffer, u16 len, void *callback) |
