PIC18F44J11 |
|
CONFIG1L (address:0x003FF8, mask:0xE1) |
|
WDTEN -- Watchdog Timer |
|
WDTEN = OFF |
0xFE |
Disabled - Controlled by SWDTEN bit. |
|
|
WDTEN = ON |
0xFF |
Enabled. |
|
|
STVREN -- Stack Overflow/Underflow Reset |
|
STVREN = OFF |
0xDF |
Disabled. |
|
|
STVREN = ON |
0xFF |
Enabled. |
|
|
XINST -- Extended Instruction Set |
|
XINST = OFF |
0xBF |
Disabled. |
|
|
XINST = ON |
0xFF |
Enabled. |
|
|
DEBUG -- Background Debug |
|
DEBUG = ON |
0x7F |
Enabled. |
|
|
DEBUG = OFF |
0xFF |
Disabled. |
|
|
CONFIG1H (address:0x003FF9, mask:0xF4) |
|
CP0 -- Code Protect |
|
CP0 = ON |
0xFB |
Program memory is code-protected. |
|
|
CP0 = OFF |
0xFF |
Program memory is not code-protected. |
|
|
CONFIG2L (address:0x003FFA, mask:0xDF) |
|
OSC -- Oscillator |
|
OSC = INTOSC |
0xF8 |
INTOSC. |
|
|
OSC = INTOSCO |
0xF9 |
INTOSCO (CLKO-RA6). |
|
|
OSC = INTOSCPLL |
0xFA |
INTOSCPLL. |
|
|
OSC = INTOSCPLLO |
0xFB |
INTOSCPLLO (CLKO-RA6). |
|
|
OSC = HS |
0xFC |
HS. |
|
|
OSC = HSPLL |
0xFD |
HS+PLL. |
|
|
OSC = EC |
0xFE |
EC (CLKO-RA6). |
|
|
OSC = ECPLL |
0xFF |
EC+PLL (CLKO-RA6). |
|
|
T1DIG -- T1OSCEN Enforcement |
|
T1DIG = OFF |
0xF7 |
Secondary Oscillator clock source may not be selected. |
|
|
T1DIG = ON |
0xFF |
Secondary Oscillator clock source may be selected. |
|
|
LPT1OSC -- Low-Power Timer1 Oscillator |
|
LPT1OSC = ON |
0xEF |
Low-power operation. |
|
|
LPT1OSC = OFF |
0xFF |
High-power operation. |
|
|
FCMEN -- Fail-Safe Clock Monitor |
|
FCMEN = OFF |
0xBF |
Disabled. |
|
|
FCMEN = ON |
0xFF |
Enabled. |
|
|
IESO -- Internal External Oscillator Switch Over Mode |
|
IESO = OFF |
0x7F |
Disabled. |
|
|
IESO = ON |
0xFF |
Enabled. |
|
|
CONFIG2H (address:0x003FFB, mask:0xFF) |
|
WDTPS -- Watchdog Postscaler |
|
WDTPS = 1 |
0xF0 |
1:1. |
|
|
WDTPS = 2 |
0xF1 |
1:2. |
|
|
WDTPS = 4 |
0xF2 |
1:4. |
|
|
WDTPS = 8 |
0xF3 |
1:8. |
|
|
WDTPS = 16 |
0xF4 |
1:16. |
|
|
WDTPS = 32 |
0xF5 |
1:32. |
|
|
WDTPS = 64 |
0xF6 |
1:64. |
|
|
WDTPS = 128 |
0xF7 |
1:128. |
|
|
WDTPS = 256 |
0xF8 |
1:256. |
|
|
WDTPS = 512 |
0xF9 |
1:512. |
|
|
WDTPS = 1024 |
0xFA |
1:1024. |
|
|
WDTPS = 2048 |
0xFB |
1:2048. |
|
|
WDTPS = 4096 |
0xFC |
1:4096. |
|
|
WDTPS = 8192 |
0xFD |
1:8192. |
|
|
WDTPS = 16384 |
0xFE |
1:16384. |
|
|
WDTPS = 32768 |
0xFF |
1:32768. |
|
|
CONFIG3L (address:0x003FFC, mask:0xFF) |
|
DSWDTOSC -- DSWDT Clock Select |
|
DSWDTOSC = T1OSCREF |
0xFE |
DSWDT uses T1OSC/T1CKI. |
|
|
DSWDTOSC = INTOSCREF |
0xFF |
DSWDT uses INTRC. |
|
|
RTCOSC -- RTCC Clock Select |
|
RTCOSC = INTOSCREF |
0xFD |
RTCC uses INTRC. |
|
|
RTCOSC = T1OSCREF |
0xFF |
RTCC uses T1OSC/T1CKI. |
|
|
DSBOREN -- Deep Sleep BOR |
|
DSBOREN = OFF |
0xFB |
Disabled. |
|
|
DSBOREN = ON |
0xFF |
Enabled. |
|
|
DSWDTEN -- Deep Sleep Watchdog Timer |
|
DSWDTEN = OFF |
0xF7 |
Disabled. |
|
|
DSWDTEN = ON |
0xFF |
Enabled. |
|
|
DSWDTPS -- Deep Sleep Watchdog Postscaler |
|
DSWDTPS = 2 |
0x0F |
1:2 (2.1 ms). |
|
|
DSWDTPS = 8 |
0x1F |
1:8 (8.3 ms). |
|
|
DSWDTPS = 32 |
0x2F |
1:32 (33 ms). |
|
|
DSWDTPS = 128 |
0x3F |
1:128 (132 ms). |
|
|
DSWDTPS = 512 |
0x4F |
1:512 (528 ms). |
|
|
DSWDTPS = 2048 |
0x5F |
1:2,048 (2.1 seconds). |
|
|
DSWDTPS = 8192 |
0x6F |
1:8,192 (8.5 seconds). |
|
|
DSWDTPS = K32 |
0x7F |
1:32,768 (34 seconds). |
|
|
DSWDTPS = K131 |
0x8F |
1:131,072 (135 seconds). |
|
|
DSWDTPS = K524 |
0x9F |
1:524,288 (9 minutes). |
|
|
DSWDTPS = M2 |
0xAF |
1:2,097,152 (36 minutes). |
|
|
DSWDTPS = M8 |
0xBF |
1:8,388,608 (2.4 hours). |
|
|
DSWDTPS = M33 |
0xCF |
1:33,554,432 (9.6 hours). |
|
|
DSWDTPS = M134 |
0xDF |
1:134,217,728 (38.5 hours). |
|
|
DSWDTPS = M536 |
0xEF |
1:536,870,912 (6.4 days). |
|
|
DSWDTPS = G2 |
0xFF |
1:2,147,483,648 (25.7 days). |
|
|
CONFIG3H (address:0x003FFD, mask:0xF9) |
|
IOL1WAY -- IOLOCK One-Way Set Enable bit |
|
IOL1WAY = OFF |
0xFE |
The IOLOCK bit (PPSCON<0>) can be set and cleared as needed. |
|
|
IOL1WAY = ON |
0xFF |
The IOLOCK bit (PPSCON<0>) can be set once. |
|
|
MSSP7B_EN -- MSSP address masking |
|
MSSP7B_EN = MSK5 |
0xF7 |
5 Bit address masking mode. |
|
|
MSSP7B_EN = MSK7 |
0xFF |
7 Bit address masking mode. |
|
|
CONFIG4L (address:0x003FFE, mask:0xCF) |
|
WPFP -- Write/Erase Protect Page Start/End Location |
|
WPFP = PAGE_0 |
0xF0 |
Write Protect Program Flash Page 0. |
|
|
WPFP = PAGE_1 |
0xF1 |
Write Protect Program Flash Page 1. |
|
|
WPFP = PAGE_2 |
0xF2 |
Write Protect Program Flash Page 2. |
|
|
WPFP = PAGE_3 |
0xF3 |
Write Protect Program Flash Page 3. |
|
|
WPFP = PAGE_4 |
0xF4 |
Write Protect Program Flash Page 4. |
|
|
WPFP = PAGE_5 |
0xF5 |
Write Protect Program Flash Page 5. |
|
|
WPFP = PAGE_6 |
0xF6 |
Write Protect Program Flash Page 6. |
|
|
WPFP = PAGE_7 |
0xF7 |
Write Protect Program Flash Page 7. |
|
|
WPFP = PAGE_8 |
0xF8 |
Write Protect Program Flash Page 8. |
|
|
WPFP = PAGE_9 |
0xF9 |
Write Protect Program Flash Page 9. |
|
|
WPFP = PAGE_10 |
0xFA |
Write Protect Program Flash Page 10. |
|
|
WPFP = PAGE_11 |
0xFB |
Write Protect Program Flash Page 11. |
|
|
WPFP = PAGE_12 |
0xFC |
Write Protect Program Flash Page 12. |
|
|
WPFP = PAGE_13 |
0xFD |
Write Protect Program Flash Page 13. |
|
|
WPFP = PAGE_14 |
0xFE |
Write Protect Program Flash Page 14. |
|
|
WPFP = PAGE_15 |
0xFF |
Write Protect Program Flash Page 15. |
|
|
WPEND -- Write/Erase Protect Region Select (valid when WPDIS = 0) |
|
WPEND = PAGE_0 |
0xBF |
Page 0 through WPFP<5:0> erase/write protected. |
|
|
WPEND = PAGE_WPFP |
0xFF |
Page WPFP<5:0> through Configuration Words erase/write protected. |
|
|
WPCFG -- Write/Erase Protect Configuration Region |
|
WPCFG = ON |
0x7F |
Configuration Words page erase/write-protected. |
|
|
WPCFG = OFF |
0xFF |
Configuration Words page not erase/write-protected. |
|
|
CONFIG4H (address:0x003FFF, mask:0xF1) |
|
WPDIS -- Write Protect Disable bit |
|
WPDIS = ON |
0xFE |
WPFP<5:0>/WPEND region erase/write protected. |
|
|
WPDIS = OFF |
0xFF |
WPFP<5:0>/WPEND region ignored. |
|