PIC18F25K50 |
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CONFIG1L (address:0x300000, mask:0x00) |
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PLLSEL -- PLL Selection |
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PLLSEL = PLL4X |
0xFE |
4x clock multiplier. |
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PLLSEL = PLL3X |
0xFF |
3x clock multiplier. |
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CFGPLLEN -- PLL Enable Configuration bit |
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CFGPLLEN = OFF |
0xFD |
PLL Disabled (firmware controlled). |
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CFGPLLEN = ON |
0xFF |
PLL Enabled. |
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CPUDIV -- CPU System Clock Postscaler |
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CPUDIV = NOCLKDIV |
0xE7 |
CPU uses system clock (no divide). |
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CPUDIV = CLKDIV2 |
0xEF |
CPU uses system clock divided by 2. |
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CPUDIV = CLKDIV3 |
0xF7 |
CPU uses system clock divided by 3. |
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CPUDIV = CLKDIV6 |
0xFF |
CPU uses system clock divided by 6. |
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LS48MHZ -- Low Speed USB mode with 48 MHz system clock |
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LS48MHZ = SYS24X4 |
0xDF |
System clock at 24 MHz, USB clock divider is set to 4. |
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LS48MHZ = SYS48X8 |
0xFF |
System clock at 48 MHz, USB clock divider is set to 8. |
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CONFIG1H (address:0x300001, mask:0x25) |
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FOSC -- Oscillator Selection |
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FOSC = LP |
0xF0 |
LP oscillator. |
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FOSC = XT |
0xF1 |
XT oscillator. |
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FOSC = HSH |
0xF2 |
HS oscillator, high power 16MHz to 25MHz. |
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FOSC = HSM |
0xF3 |
HS oscillator, medium power 4MHz to 16MHz. |
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FOSC = ECHCLKO |
0xF4 |
EC oscillator, high power 16MHz to 48MHz, clock output on OSC2. |
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FOSC = ECHIO |
0xF5 |
EC oscillator, high power 16MHz to 48MHz. |
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FOSC = RCCLKO |
0xF6 |
External RC oscillator, clock output on OSC2. |
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FOSC = RCIO |
0xF7 |
External RC oscillator. |
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FOSC = INTOSCIO |
0xF8 |
Internal oscillator. |
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FOSC = INTOSCCLKO |
0xF9 |
Internal oscillator, clock output on OSC2. |
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FOSC = ECMCLKO |
0xFA |
EC oscillator, medium power 4MHz to 16MHz, clock output on OSC2. |
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FOSC = ECMIO |
0xFB |
EC oscillator, medium power 4MHz to 16MHz. |
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FOSC = ECLCLKO |
0xFC |
EC oscillator, low power <4MHz, clock output on OSC2. |
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FOSC = ECLIO |
0xFD |
EC oscillator, low power <4MHz. |
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PCLKEN -- Primary Oscillator Shutdown |
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PCLKEN = OFF |
0xDF |
Primary oscillator shutdown firmware controlled. |
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PCLKEN = ON |
0xFF |
Primary oscillator enabled. |
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FCMEN -- Fail-Safe Clock Monitor |
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FCMEN = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
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FCMEN = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
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IESO -- Internal/External Oscillator Switchover |
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IESO = OFF |
0x7F |
Oscillator Switchover mode disabled. |
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IESO = ON |
0xFF |
Oscillator Switchover mode enabled. |
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CONFIG2L (address:0x300002, mask:0x5F) |
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nPWRTEN -- Power-up Timer Enable |
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nPWRTEN = ON |
0xFE |
Power up timer enabled. |
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nPWRTEN = OFF |
0xFF |
Power up timer disabled. |
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BOREN -- Brown-out Reset Enable |
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BOREN = OFF |
0xF9 |
BOR disabled in hardware (SBOREN is ignored). |
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BOREN = ON |
0xFB |
BOR controlled by firmware (SBOREN is enabled). |
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BOREN = NOSLP |
0xFD |
BOR enabled in hardware, disabled in Sleep mode (SBOREN is ignored). |
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BOREN = SBORDIS |
0xFF |
BOR enabled in hardware (SBOREN is ignored). |
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BORV -- Brown-out Reset Voltage |
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BORV = 285 |
0xE7 |
BOR set to 2.85V nominal. |
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BORV = 250 |
0xEF |
BOR set to 2.5V nominal. |
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BORV = 220 |
0xF7 |
BOR set to 2.2V nominal. |
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BORV = 190 |
0xFF |
BOR set to 1.9V nominal. |
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nLPBOR -- Low-Power Brown-out Reset |
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nLPBOR = ON |
0xBF |
Low-Power Brown-out Reset enabled. |
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nLPBOR = OFF |
0xFF |
Low-Power Brown-out Reset disabled. |
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CONFIG2H (address:0x300003, mask:0x3F) |
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WDTEN -- Watchdog Timer Enable bits |
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WDTEN = OFF |
0xFC |
WDT disabled in hardware (SWDTEN ignored). |
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WDTEN = NOSLP |
0xFD |
WDT enabled in hardware, disabled in Sleep mode (SWDTEN ignored). |
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WDTEN = SWON |
0xFE |
WDT controlled by firmware (SWDTEN enabled). |
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WDTEN = ON |
0xFF |
WDT enabled in hardware (SWDTEN ignored). |
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WDTPS -- Watchdog Timer Postscaler |
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WDTPS = 1 |
0xC3 |
1:1. |
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WDTPS = 2 |
0xC7 |
1:2. |
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WDTPS = 4 |
0xCB |
1:4. |
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WDTPS = 8 |
0xCF |
1:8. |
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WDTPS = 16 |
0xD3 |
1:16. |
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WDTPS = 32 |
0xD7 |
1:32. |
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WDTPS = 64 |
0xDB |
1:64. |
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WDTPS = 128 |
0xDF |
1:128. |
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WDTPS = 256 |
0xE3 |
1:256. |
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WDTPS = 512 |
0xE7 |
1:512. |
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WDTPS = 1024 |
0xEB |
1:1024. |
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WDTPS = 2048 |
0xEF |
1:2048. |
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WDTPS = 4096 |
0xF3 |
1:4096. |
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WDTPS = 8192 |
0xF7 |
1:8192. |
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WDTPS = 16384 |
0xFB |
1:16384. |
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WDTPS = 32768 |
0xFF |
1:32768. |
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CONFIG3H (address:0x300005, mask:0xD3) |
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CCP2MX -- CCP2 MUX bit |
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CCP2MX = RB3 |
0xFE |
CCP2 input/output is multiplexed with RB3. |
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CCP2MX = RC1 |
0xFF |
CCP2 input/output is multiplexed with RC1. |
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PBADEN -- PORTB A/D Enable bit |
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PBADEN = OFF |
0xFD |
PORTB<5:0> pins are configured as digital I/O on Reset. |
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PBADEN = ON |
0xFF |
PORTB<5:0> pins are configured as analog input channels on Reset. |
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T3CMX -- Timer3 Clock Input MUX bit |
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T3CMX = RB5 |
0xEF |
T3CKI function is on RB5. |
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T3CMX = RC0 |
0xFF |
T3CKI function is on RC0. |
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SDOMX -- SDO Output MUX bit |
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SDOMX = RC7 |
0xBF |
SDO function is on RC7. |
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SDOMX = RB3 |
0xFF |
SDO function is on RB3. |
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MCLRE -- Master Clear Reset Pin Enable |
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MCLRE = OFF |
0x7F |
RE3 input pin enabled; external MCLR disabled. |
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MCLRE = ON |
0xFF |
MCLR pin enabled; RE3 input disabled. |
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CONFIG4L (address:0x300006, mask:0xA5) |
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STVREN -- Stack Full/Underflow Reset |
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STVREN = OFF |
0xFE |
Stack full/underflow will not cause Reset. |
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STVREN = ON |
0xFF |
Stack full/underflow will cause Reset. |
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LVP -- Single-Supply ICSP Enable bit |
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LVP = OFF |
0xFB |
Single-Supply ICSP disabled. |
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LVP = ON |
0xFF |
Single-Supply ICSP enabled if MCLRE is also 1. |
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XINST -- Extended Instruction Set Enable bit |
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XINST = OFF |
0xBF |
Instruction set extension and Indexed Addressing mode disabled. |
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XINST = ON |
0xFF |
Instruction set extension and Indexed Addressing mode enabled. |
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DEBUG -- Background Debugger Enable bit |
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DEBUG = ON |
0x7F |
Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug. |
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DEBUG = OFF |
0xFF |
Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins. |
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CONFIG5L (address:0x300008, mask:0x0F) |
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CP0 -- Block 0 Code Protect |
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CP0 = ON |
0xFE |
Block 0 is code-protected. |
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CP0 = OFF |
0xFF |
Block 0 is not code-protected. |
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CP1 -- Block 1 Code Protect |
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CP1 = ON |
0xFD |
Block 1 is code-protected. |
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CP1 = OFF |
0xFF |
Block 1 is not code-protected. |
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CP2 -- Block 2 Code Protect |
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CP2 = ON |
0xFB |
Block 2 is code-protected. |
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CP2 = OFF |
0xFF |
Block 2 is not code-protected. |
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CP3 -- Block 3 Code Protect |
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CP3 = ON |
0xF7 |
Block 3 is code-protected. |
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CP3 = OFF |
0xFF |
Block 3 is not code-protected. |
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CONFIG5H (address:0x300009, mask:0xC0) |
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CPB -- Boot Block Code Protect |
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CPB = ON |
0xBF |
Boot block is code-protected. |
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CPB = OFF |
0xFF |
Boot block is not code-protected. |
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CPD -- Data EEPROM Code Protect |
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CPD = ON |
0x7F |
Data EEPROM is code-protected. |
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CPD = OFF |
0xFF |
Data EEPROM is not code-protected. |
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CONFIG6L (address:0x30000A, mask:0x0F) |
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WRT0 -- Block 0 Write Protect |
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WRT0 = ON |
0xFE |
Block 0 (0800-1FFFh) is write-protected. |
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WRT0 = OFF |
0xFF |
Block 0 (0800-1FFFh) is not write-protected. |
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WRT1 -- Block 1 Write Protect |
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WRT1 = ON |
0xFD |
Block 1 (2000-3FFFh) is write-protected. |
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WRT1 = OFF |
0xFF |
Block 1 (2000-3FFFh) is not write-protected. |
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WRT2 -- Block 2 Write Protect |
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WRT2 = ON |
0xFB |
Block 2 (04000-5FFFh) is write-protected. |
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WRT2 = OFF |
0xFF |
Block 2 (04000-5FFFh) is not write-protected. |
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WRT3 -- Block 3 Write Protect |
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WRT3 = ON |
0xF7 |
Block 3 (06000-7FFFh) is write-protected. |
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WRT3 = OFF |
0xFF |
Block 3 (06000-7FFFh) is not write-protected. |
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CONFIG6H (address:0x30000B, mask:0xE0) |
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WRTC -- Configuration Registers Write Protect |
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WRTC = ON |
0xDF |
Configuration registers (300000-3000FFh) are write-protected. |
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WRTC = OFF |
0xFF |
Configuration registers (300000-3000FFh) are not write-protected. |
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WRTB -- Boot Block Write Protect |
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WRTB = ON |
0xBF |
Boot block (0000-7FFh) is write-protected. |
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WRTB = OFF |
0xFF |
Boot block (0000-7FFh) is not write-protected. |
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WRTD -- Data EEPROM Write Protect |
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WRTD = ON |
0x7F |
Data EEPROM is write-protected. |
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WRTD = OFF |
0xFF |
Data EEPROM is not write-protected. |
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CONFIG7L (address:0x30000C, mask:0x0F) |
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EBTR0 -- Block 0 Table Read Protect |
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EBTR0 = ON |
0xFE |
Block 0 is protected from table reads executed in other blocks. |
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EBTR0 = OFF |
0xFF |
Block 0 is not protected from table reads executed in other blocks. |
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EBTR1 -- Block 1 Table Read Protect |
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EBTR1 = ON |
0xFD |
Block 1 is protected from table reads executed in other blocks. |
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EBTR1 = OFF |
0xFF |
Block 1 is not protected from table reads executed in other blocks. |
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EBTR2 -- Block 2 Table Read Protect |
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EBTR2 = ON |
0xFB |
Block 2 is protected from table reads executed in other blocks. |
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EBTR2 = OFF |
0xFF |
Block 2 is not protected from table reads executed in other blocks. |
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EBTR3 -- Block 3 Table Read Protect |
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EBTR3 = ON |
0xF7 |
Block 3 is protected from table reads executed in other blocks. |
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EBTR3 = OFF |
0xFF |
Block 3 is not protected from table reads executed in other blocks. |
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CONFIG7H (address:0x30000D, mask:0x40) |
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EBTRB -- Boot Block Table Read Protect |
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EBTRB = ON |
0xBF |
Boot block is protected from table reads executed in other blocks. |
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EBTRB = OFF |
0xFF |
Boot block is not protected from table reads executed in other blocks. |
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