PIC18F1330 |
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CONFIG1H (address:0x300001, mask:0x07) |
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OSC -- Oscillator |
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OSC = LP |
0xF0 |
LP Oscillator. |
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OSC = XT |
0xF1 |
XT Oscillator. |
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OSC = HS |
0xF2 |
HS Oscillator. |
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OSC = RC |
0xF3 |
External RC oscillator, CLKO function on RA6. |
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OSC = EC |
0xF4 |
EC oscillator, CLKO function on RA6. |
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OSC = ECIO |
0xF5 |
EC oscillator, port function on RA6. |
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OSC = HSPLL |
0xF6 |
HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1). |
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OSC = RCIO |
0xF7 |
External RC oscillator, port function on RA6. |
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OSC = INTIO2 |
0xF8 |
Internal oscillator, port function on RA6 and RA7. |
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OSC = INTIO1 |
0xF9 |
Internal oscillator, CLKO function on RA6, port function on RA7. |
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FCMEN -- Fail-Safe Clock Monitor Enable bit |
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FCMEN = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
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FCMEN = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
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IESO -- Internal/External Oscillator Switchover bit |
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IESO = OFF |
0x7F |
Oscillator Switchover mode disabled. |
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IESO = ON |
0xFF |
Oscillator Switchover mode enabled. |
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CONFIG2L (address:0x300002, mask:0x1F) |
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PWRT -- Power-up Timer Enable bit |
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PWRT = ON |
0xFE |
PWRT enabled. |
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PWRT = OFF |
0xFF |
PWRT disabled. |
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BOR -- Brown-out Reset Enable bits |
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BOR = OFF |
0xF9 |
Brown-out Reset disabled in hardware and software. |
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BOR = SBORENCTRL |
0xFB |
Brown-out Reset enabled and controlled by software (SBOREN is enabled). |
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BOR = BOACTIVE |
0xFD |
Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled). |
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BOR = BOHW |
0xFF |
Brown-out Reset enabled in hardware only (SBOREN is disabled). |
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BORV -- Brown-out Reset Voltage bits |
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BORV = 0 |
0xE7 |
Maximum setting. |
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BORV = 1 |
0xEF |
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BORV = 2 |
0xF7 |
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BORV = 3 |
0xFF |
Minimum setting. |
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CONFIG2H (address:0x300003, mask:0x1F) |
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WDT -- Watchdog Timer Enable bit |
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WDT = OFF |
0xFE |
WDT disabled (control is placed on the SWDTEN bit). |
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WDT = ON |
0xFF |
WDT enabled. |
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WDTPS -- Watchdog Timer Postscale Select bits |
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WDTPS = 1 |
0xE1 |
1:1. |
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WDTPS = 2 |
0xE3 |
1:2. |
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WDTPS = 4 |
0xE5 |
1:4. |
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WDTPS = 8 |
0xE7 |
1:8. |
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WDTPS = 16 |
0xE9 |
1:16. |
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WDTPS = 32 |
0xEB |
1:32. |
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WDTPS = 64 |
0xED |
1:64. |
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WDTPS = 128 |
0xEF |
1:128. |
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WDTPS = 256 |
0xF1 |
1:256. |
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WDTPS = 512 |
0xF3 |
1:512. |
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WDTPS = 1024 |
0xF5 |
1:1024. |
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WDTPS = 2048 |
0xF7 |
1:2048. |
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WDTPS = 4096 |
0xF9 |
1:4096. |
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WDTPS = 8192 |
0xFB |
1:8192. |
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WDTPS = 16384 |
0xFD |
1:16384. |
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WDTPS = 32768 |
0xFF |
1:32768. |
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CONFIG3L (address:0x300004, mask:0x0E) |
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PWMPIN -- PWM Output Pins Reset State Control bit |
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PWMPIN = ON |
0xFD |
PWM outputs drive active states upon Reset. |
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PWMPIN = OFF |
0xFF |
PWM outputs disabled upon Reset. |
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LPOL -- Low-Side Transistors Polarity bit (Even PWM Output Polarity Control bit) |
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LPOL = LOW |
0xFB |
PWM0, PWM2 and PWM4 are active-low. |
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LPOL = HIGH |
0xFF |
PWM0, PWM2 and PWM4 are active-high (default). |
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HPOL -- High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit) |
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HPOL = LOW |
0xF7 |
PWM1, PWM3 and PWM5 are active-low. |
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HPOL = HIGH |
0xFF |
PWM1, PWM3 and PWM5 are active-high (default). |
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CONFIG3H (address:0x300005, mask:0x81) |
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FLTAMX -- FLTA Mux bit |
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FLTAMX = RA7 |
0xFE |
FLTA input is muxed onto RA7. |
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FLTAMX = RA5 |
0xFF |
FLTA input is muxed onto RA5. |
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T1OSCMX -- T1OSO/T1CKI MUX bit |
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T1OSCMX = LOW |
0xF7 |
T1OSO/T1CKI pin resides on RB2. |
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T1OSCMX = HIGH |
0xFF |
T1OSO/T1CKI pin resides on RA6. |
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MCLRE -- Master Clear Enable bit |
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MCLRE = OFF |
0x7F |
RA5 input pin enabled, MCLR pin disabled. |
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MCLRE = ON |
0xFF |
MCLR pin enabled, RA5 input pin disabled. |
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CONFIG4L (address:0x300006, mask:0x81) |
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STVREN -- Stack Overflow/Underflow Reset Enable bit |
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STVREN = OFF |
0xFE |
Reset on stack overflow/underflow disabled. |
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STVREN = ON |
0xFF |
Reset on stack overflow/underflow enabled. |
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BBSIZ -- Boot Block Size Select bits |
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BBSIZ = BB256 |
0xCF |
256 Words (512 Bytes) Boot Block size. |
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BBSIZ = BB512 |
0xDF |
512 Words (1024 Bytes) Boot Block size. |
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BBSIZ = BB1K |
0xFF |
1K Words (2048 Bytes) Boot Block size. |
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XINST -- Extended Instruction Set Enable bit |
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XINST = OFF |
0xBF |
Instruction set extension and Indexed Addressing mode disabled. |
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XINST = ON |
0xFF |
Instruction set extension and Indexed Addressing mode enabled. |
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DEBUG -- Background Debugger Enable bit |
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DEBUG = ON |
0x7F |
Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug. |
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DEBUG = OFF |
0xFF |
Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins. |
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CONFIG5L (address:0x300008, mask:0x03) |
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CP0 -- Code Protection bit Block 0 (000800-000FFF) |
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CP0 = ON |
0xFE |
Block 0 is code-protected. |
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CP0 = OFF |
0xFF |
Block 0 is not code-protected. |
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CP1 -- Code Protection bit Block 1 (001000-001FFF) |
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CP1 = ON |
0xFD |
Block 1 is code-protected. |
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CP1 = OFF |
0xFF |
Block 1 is not code-protected. |
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CONFIG5H (address:0x300009, mask:0xC0) |
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CPB -- Code Protection bit (Boot Block Memory Area) |
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CPB = ON |
0xBF |
Boot Block is code-protected. |
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CPB = OFF |
0xFF |
Boot Block is not code-protected. |
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CPD -- Code Protection bit (Data EEPROM) |
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CPD = ON |
0x7F |
Data EEPROM is code-protected. |
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CPD = OFF |
0xFF |
Data EEPROM is not code-protected. |
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CONFIG6L (address:0x30000A, mask:0x03) |
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WRT0 -- Write Protection bit Block 0 (000800-000FFF) |
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WRT0 = ON |
0xFE |
Block 0 is write-protected. |
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WRT0 = OFF |
0xFF |
Block 0 is not write-protected. |
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WRT1 -- Write Protection bit Block 1 (001000-001FFF) |
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WRT1 = ON |
0xFD |
Block 1 is write-protected. |
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WRT1 = OFF |
0xFF |
Block 1 is not write-protected. |
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CONFIG6H (address:0x30000B, mask:0xE0) |
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WRTC -- Write Protection bit (Configuration Registers) |
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WRTC = ON |
0xDF |
Configuration registers are write-protected. |
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WRTC = OFF |
0xFF |
Configuration registers are not write-protected. |
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WRTB -- Write Protection bit (Boot Block Memory Area) |
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WRTB = ON |
0xBF |
Boot Block is write-protected. |
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WRTB = OFF |
0xFF |
Boot Block is not write-protected. |
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WRTD -- Write Protection bit (Data EEPROM) |
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WRTD = ON |
0x7F |
Data EEPROM is write-protected. |
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WRTD = OFF |
0xFF |
Data EEPROM is not write-protected. |
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CONFIG7L (address:0x30000C, mask:0x03) |
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EBTR0 -- Table Read Protection bit Block 0 (000800-000FFF) |
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EBTR0 = ON |
0xFE |
Block 0 is protected from table reads executed in other blocks. |
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EBTR0 = OFF |
0xFF |
Block 0 is not protected from table reads executed in other blocks. |
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EBTR1 -- Table Read Protection bit Block 1 (001000-001FFF) |
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EBTR1 = ON |
0xFD |
Block 1 is protected from table reads executed in other blocks. |
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EBTR1 = OFF |
0xFF |
Block 1 is not protected from table reads executed in other blocks. |
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CONFIG7H (address:0x30000D, mask:0x40) |
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EBTRB -- Table Read Protection bit (Boot Block Memory Area) |
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EBTRB = ON |
0xBF |
Boot Block is protected from table reads executed in other blocks. |
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EBTRB = OFF |
0xFF |
Boot Block is not protected from table reads executed in other blocks. |
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