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mb_olre16 [2016/09/23 20:18]
psykhaze [GrayScale Clock]
mb_olre16 [2016/09/24 16:30]
antichambre [Sizing]
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 We expect 16 RGB LED rings encoders. So let's do the math : We expect 16 RGB LED rings encoders. So let's do the math :
 **16 Encoders * 32 LEDs * 3 colors = __1536 lines__ ** \\ **16 Encoders * 32 LEDs * 3 colors = __1536 lines__ ** \\
-Let's transpose this to a classical matrixed SRIO chain design:  +Let's transpose this to a classical matrixed SRIO chain design: ​\\ 
-**3x16=48 inputs + 32 outputs = __6*DIN + 4*DOUT__ **\\ +** 16 * 3 (cathodes) * 32 (anodes)** \\ 
 +**= 48 inputs + 32 outputs ​** \\ 
 +**= __6*DIN + 4*DOUT__ **\\
 ==== Core-External Driving Concept : TLC5958 ==== ==== Core-External Driving Concept : TLC5958 ====
  
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 ==== Data Transfer ==== ==== Data Transfer ====
   ​   ​
-A serialized design has been chosen to provide data to TLC. Prototype feature only 2 steps but the CORE works like there'​s 4 modules of 16 steps connected. In order to benchmark reactivity and Transfer time, Core send data for 4 modules. Through an emulated software SPI bus, for this 64 rings Data Sending __takes less than 5ms__ . Different colors and patterns like relative value(-64/​63),​ keyboard(B&​W keys) etc... were tested.\\+A serialized design has been chosen to provide data to TLC. Prototype feature only 2 steps but the CORE works like there'​s 4 modules of 16 steps connected. In order to benchmark reactivity and Transfer time, Core send data for 4 modules(4*16*32*3*16bit=12KBytes). Through an emulated software SPI bus, for this 64 rings Data Sending __takes less than 5ms__ . Different colors and patterns like relative value(-64/​63),​ keyboard(B&​W keys) etc... were tested.\\
  
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 {{antichambre:​large.img_3754.jpg?​300|}} ​  ​{{:​antichambre:​large.3653bd.jpeg?​460|}}\\ {{antichambre:​large.img_3754.jpg?​300|}} ​  ​{{:​antichambre:​large.3653bd.jpeg?​460|}}\\
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 ==== GrayScale Clock ==== ==== GrayScale Clock ====
  
mb_olre16.txt · Last modified: 2019/04/21 08:50 by antichambre