pad_4_4
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pad_4_4 [2016/08/10 22:04] – [Schematic] latigid_on | pad_4_4 [2018/03/05 22:57] (current) – [Assembly] latigid_on | ||
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===== Schematic ===== | ===== Schematic ===== | ||
- | {{: | + | {{: |
//Rear view// | //Rear view// | ||
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The pLED chain enters via J2:pin 6 and resistor R1. The resistor should be replaced with a wire link for each additional module (i.e. only the first in the chain gets a resistor, the remainder stuffed with wire links). The serial chain then follows a snake pattern to J3, where additional pLED modules may be connected. The RC (R2, C18) end termination shouldn' | The pLED chain enters via J2:pin 6 and resistor R1. The resistor should be replaced with a wire link for each additional module (i.e. only the first in the chain gets a resistor, the remainder stuffed with wire links). The serial chain then follows a snake pattern to J3, where additional pLED modules may be connected. The RC (R2, C18) end termination shouldn' | ||
- | {{:: | + | {{:: |
//Front view// | //Front view// | ||
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- | ===== BOM v1.2 ===== | + | ===== BOM v1.1 ===== |
^Type | ^Type | ||
^resistors^ | ^resistors^ | ||
- | | |20 |49k9 |0204/7|R1, R2, R4, R5, R6, R7, R8, R10, R11, R12, R13, R14, R16, R17, R18, R19, R20, R22, R23, R24| | + | | |1 |220-470R |
- | | | + | |
^capacitors^ | ^capacitors^ | ||
- | | |4|10p|025X050|C1, C3, C5, C7| | + | | |16|100n|1206|C2-17| |
- | | |9|100n|025X050|C10, | + | | |1|100-1000u|electrolytic |
- | | |3|10u|electrolytic 2,5-6|C9, C11, C19|remove 1 if powering from Core| | + | ^diodes^ |
- | | |4|optional|025X050|C2, | + | | |1|1N5187|DO41-7.6|D1| |
- | ^inductors^ | + | | |16|1N4148|DO41-7.6|remaining axial diodes| |
- | | |2|BEAD|5MM|L1, L2| | + | | |16|WS2812B|5mm|programmable LEDs| |
- | ^ICs^ | + | |
- | | |2|MCP6002P|DIL08|IC2, IC4|sockets are recommended| | + | |
- | | |2|TL072P|DIL08|IC1, IC3|sockets are recommended| | + | |
- | ^Vreg^ | + | |
- | | |1|optional|TO-220|VR1|remove if powering from Core| | + | |
^headers^ | ^headers^ | ||
- | | |7| |1X02_SMALL|JP1, JP2, JP3, JP4, JP5, JP6, JP7|check board for headers as SIL strips | + | | |4| |2*5 (shrouded) SMT|J2-5|can use DIL 100mil breakaway header |
- | | |8| |1X03_SMALL|JP8, JP9, JP10, JP11, JP12, JP13, JP14, JP15| | + | | |1| |
- | | |2| |2*5 (shrouded)|J1, J2| | + | ^switches^ |
+ | | |1| |Sparkfun 4x4 pad| | ||
+ | ^misc^ | ||
+ | | |1| |acrylic bezel| | ||
===== Versions ===== | ===== Versions ===== | ||
- | + | v1.1: current | |
- | v1.2: first release. | + | v1.0: errata: J4 and J5 have no connection to ground. J1-3 do carry ground, so it isn't a problem if the DIN/DOUT modules share the same power rail. |
===== Assembly ===== | ===== Assembly ===== | ||
- | Putting | + | To keep the button pad flat, it's best to solder all components on the rear of the board i.e. opposite the pads. The contacts are exposed ENIG, so try not to damage |
- | ==== Resistors ==== | + | Start by tinning one pad (preferably not the pad joined to the ground plane with thermals) of each 1206 capacitor, making a " |
- | | + | The best way to fix the 1N4148 diodes is to place the parts then solder |
- | | + | |
- | | + | |
- | | + | |
- | {{: | + | Check that the pinout of your pLEDs matches with the board i.e. serial in on the rounded side, serial out on the flattened side. Also test the height relative to the silicone button pad; it's not necessary to push the leads in the whole way (and you might damage your LED). |
- | ==== Capacitors ==== | + | If using shrouded headers, ensure the notch points out on the same side as the pin 1 designator. |
- | * four 10p as marked in pink | ||
- | * electrolytics in yellow | ||
- | * blue are optional (i.e. probably unnecessary) | ||
- | * remainder are 100n. | ||
- | {{: | ||
- | ==== Power ==== | + | ==== Interconnections |
- | + | ||
- | * J2 is a standard Eurorack header | + | |
- | * red = -12V | + | |
- | * blue = +12V | + | |
- | * green = 0V(ground) | + | |
- | * for Core power, bridge the solder jumper marked in yellow | + | |
- | * otherwise install the Vreg circuit in pink | + | |
- | * **IMPORTANT** only choose one of these 3v3 power options! Don't install the regulator if the solder jumper is bridged. | + | |
- | + | ||
- | {{: | + | |
- | + | ||
- | ==== Headers ==== | + | |
- | + | ||
- | For connection to a [[Control Board]], use pin headers placed on the opposite side as the rest of the components i.e. follow the silkscreen markings. For standalone use, you probably want header pins (or sockets, or even bare wires if you wish) on the same side as the remaining circuitry. | + | |
- | + | ||
- | ---- | + | |
- | + | ||
- | + | ||
- | ==== Standalone use ==== | + | |
- | + | ||
- | For simplest results, use the complementary [[Control Board]]. Otherwise see below for header functions. | + | |
- | + | ||
- | + | ||
- | === Five pin header === | + | |
- | + | ||
- | * IN = CV input | + | |
- | * for scaling bipolar CVs, connect or switch into OFFSET (e.g. +5V; n.b. the offset should be referenced to the common 0V) | + | |
- | * for 0-5V operation, leave SWITCH open; for 0-10V operation, jumper or switch in COMMON to POLE | + | |
- | + | ||
- | {{: | + | |
- | + | ||
- | + | ||
- | + | ||
- | + | ||
- | === Three pin header === | + | |
- | + | ||
- | * with a 100k pot facing you, solder the left leg to 0V(ground) | + | |
- | * centre to WIPER | + | |
- | * right to LEG | + | |
- | * WIPER and LEG may be jumpered if pots aren't desired, but it is quite useful to have an attenuator to trim down variable CVs or even clip the second op amp for crunchy waveforms! | + | |
- | + | ||
- | {{: | + | |
- | ---- | + | |
- | + | ||
- | ==== Interconnection to Core ==== | + | |
- | + | ||
- | J1 carries the scaled CV to J5A or J5B of an STM32F4 Core module. | + | |
- | ---- | + | |
+ | * J2 normally connects to Core J4B (I2C) | ||
+ | * J3 carries the WS2812B chain for additional modules | ||
+ | * J4 connects to a DIN header | ||
+ | * J5 connects to a DOUT header | ||
- | ==== License ==== | + | ===== License |
Currently the design is (c) 2016 antilog devices with all rights reserved; all documentation is CC BY-NC-SA 3.0. | Currently the design is (c) 2016 antilog devices with all rights reserved; all documentation is CC BY-NC-SA 3.0. |
pad_4_4.1470866694.txt.gz · Last modified: 2016/08/10 22:04 by latigid_on