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--- mb_olre16 [2016/09/23 15:29]
psykhaze
+++ mb_olre16 [2016/09/25 07:53]
antichambre [GrayScale Clock]
@@ Line 30: / Line 30: @@
 We expect 16 RGB LED rings encoders. So let's do the math :
 **16 Encoders * 32 LEDs * 3 colors = __1536 lines__ ** \\
-Let's transpose this to a classical matrixed SRIO chain design:
+Let's transpose this to a classical matrixed SRIO chain design: \\
-**3x16=48 inputs + 32 outputs = __6*DIN + 4*DOUT__ **\\
+** 16 * 3 (cathodes) * 32 (anodes)** \\
+**= 48 inputs + 32 outputs ** \\
+**= __6*DIN + 4*DOUT__ **\\
 ==== Core-External Driving Concept : TLC5958 ====
-In theory it's possible to drive such a SRIO setup but in fact buses and resistors/R networs are very hard to place and will consume a lot of process. \\
+In theory it's possible to drive such a SRIO setup but in fact buses and resistors/R networks are very hard to place and it will consume a lot of contant refresh process. \\
 \\
 After a look on the different brands and models of LED driver IC **[[http://www.ti.com/product/TLC5958|Texas Instruments TLC5958]]** appeared as a good compromise to drive a lot of RGB LEDs without overloading the core. Designed to be a LED Display driver, its original purpose and features would allow large-sized RGB-LED-based display setups\\
+\\
+**<wrap download>{{http://www.ti.com/lit/ds/symlink/tlc5958.pdf|TLC5958 Datasheet}}</wrap>**
+\\
+\\
 This Design note from Texas Instruments helps in understanding how to design around the TLC:\\
 **<wrap download>{{:antichambre:slva645_5_.pdf|Build high density, high refresh rate, multiplexing LED panel with TLC5958}}</wrap>**
@@ Line 97: / Line 101: @@
 ==== Data Transfer ====
-A serialized design has been chosen to provide data to TLC. Prototype feature only 2 steps but the CORE works like there's 4 modules of 16 steps connected. In order to benchmark reactivity and Transfer time, Core send data for 4 modules. Through an emulated software SPI bus, for this 64 rings Data Sending __takes less than 5ms__ . Different colors and patterns like relative value(-64/63), keyboard(B&W keys) etc... were tested.\\
+A serialized design has been chosen to provide data to TLC. Prototype feature only 2 steps but the CORE works like there's 4 modules of 16 steps connected. In order to benchmark reactivity and Transfer time, Core send data for 4 modules(4*16*32*3*16bit=12KBytes). Through an emulated software SPI bus, for this 64 rings Data Sending __takes less than 5ms__ . Different colors and patterns like relative value(-64/63), keyboard(B&W keys) etc... were tested.\\
 {{antichambre:img_3658.jpg?300|}}{{:antichambre:img_3657.jpg?300|}}{{antichambre:img_3656.jpg?300|}}\\
 {{antichambre:large.img_3754.jpg?300|}}   {{:antichambre:large.3653bd.jpeg?460|}}\\
 ==== GrayScale Clock ====
-Design of External GrayScale Clock for the TLC was tricky.
+Design of External GrayScale Clock for the TLC was tricky.\\
-clock periods and halt for some 1.5~2.5µs are needed for each address line . TLC would receive a VSYNC command at the end of the 32th address line to prepare the new frame datas. \\
+\\
+**257 clock periods and halt for some 1.5~2.5µs are needed for each address line** \\
+\\
+TLC would receive a VSYNC command at the end of the 32th address line to prepare the new frame datas. \\
 \\
 The first approach was to provide a PWM at 800KHz and put it back to the LPC on a TMR CAP Input, use 2 MAT outputs to provide a line period and gate(NOR) the PWM with it.\\
-First issue, halting time after the 257 periods wasn't constant and dependent of PWM frequency.2nd issue, much I/O used only for this purpose.\\
+\\
+//First issue, halting time after the 257 periods wasn't constant and dependent of PWM frequency. Second issue, much I/O used only for this purpose.//\\
@@ Line 119: / Line 126: @@
 {{:antichambre:slva645_5_2.png?800|}}\\
-TLC is wired like on an SPI bus to Core Board. Here are equivalences:\\
+TLC is wired like on an SPI bus to Core Board. Here are connections equivalences:\\
   * SCLK => SC
   * DATA => SO
   * LAT => RC
   * FLAGS READ => SI
+**[[stm32f4_module#inputs_outputs_ports|STM32F4 I/O Ports]]**
+\\
+\\
 //Note: Command is coded by putting LAT active during a defined number of SCLK periods.For example for a VSYNC command, LAT must be high during 3 SCLK pulses.//\\
@@ Line 134: / Line 143: @@
 ==== GrayScale Clock ====
-The TLC needs a GrayScale Clock(GSCLK) and additional control to multiplex 32 addresses (named COMSELx in previous diagram). The GSCLK signal should be 257 pulses + 1.5~2.5µs of interval between segments . COMSEL management needs 32 multiplexing adress lines for (5 bits coded and decoded directly on the top board).\\
+The TLC needs a GrayScale Clock(GSCLK) and additional control to multiplex 32 addresses (named COMSELx in diagram). The GSCLK signal should be 257 pulses + 1.5~2.5µs of interval between segments . COMSEL management needs 32 multiplexing adress lines for (5 bits coded and decoded directly on the top board).\\
 === Clock Schematic ===
@@ Line 140: / Line 149: @@
 {{:antichambre:tlc_gsclk.png?800|}}\\
-Tthe external clock circuit was simulated on LTSpice first and tested on veroboard with the prototyped OLRE16.\\
+The external clock circuit was simulated on LTSpice first and tested on veroboard with the prototyped OLRE16.\\
 PWM_CLK, RESET and EOF are connected to the CORE\\
 \\
-The CORE provides a regular Clock with PWM @2MHz .The 12bit counter U16 counts until 257 and trigs U1 wich is a monostable, U1 switchs, resets the counter and stops the clock counter input by U17(D-Flipflop). \\
+CORE provides a regular Clock with PWM @2MHz .The 12bit counter U16 counts until 257 and trigs U1 wich is a monostable, U1 switchs, resets the counter and stops the clock counter input by U17(D-Flipflop). \\
+\\
+After a certain time given by the RC couple on U1, U1 switchs back and restarts the counter.
+By this way we are sure to count the exact 257 Clocks needed and the interval between 2 segments is fixed by the trimpot U19.\\
 \\
-After a certain time given by the RC couple on U1, U1 switch back and restarts the counter.
-By this way we are sure to count the exact 257 Clocks needed and the interval between 2 segments is fixed by the trimpot U19.
 **GSCLK signal is then high during the 257 clocks period and low during the interval**\\
 === Multiplexing Schematic ===
-{{:antichambre:tlc_gsclk_topb.png?800|}}\\
+{{:antichambre:tlc_gsclk_topb.png?500|}}\\
 ADDR_x, ADDR_CLK, GSCLK are connected to the top board...\\

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