mb_olre16
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mb_olre16 [2016/09/23 19:59] psykhaze [Core-External Driving Concept : TLC5958] |
mb_olre16 [2016/09/25 07:53] antichambre [GrayScale Clock] |
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| We expect 16 RGB LED rings encoders. So let's do the math : | We expect 16 RGB LED rings encoders. So let's do the math : | ||
| **16 Encoders * 32 LEDs * 3 colors = __1536 lines__ ** \\ | **16 Encoders * 32 LEDs * 3 colors = __1536 lines__ ** \\ | ||
| - | Let's transpose this to a classical matrixed SRIO chain design: | + | Let's transpose this to a classical matrixed SRIO chain design: \\ |
| - | **3x16=48 inputs + 32 outputs = __6*DIN + 4*DOUT__ **\\ | + | ** 16 * 3 (cathodes) * 32 (anodes)** \\ |
| + | **= 48 inputs + 32 outputs ** \\ | ||
| + | **= __6*DIN + 4*DOUT__ **\\ | ||
| ==== Core-External Driving Concept : TLC5958 ==== | ==== Core-External Driving Concept : TLC5958 ==== | ||
| - | In theory it's possible to drive such a SRIO setup but in fact buses and resistors/R networs are very hard to place and will consume a lot of process. \\ | + | In theory it's possible to drive such a SRIO setup but in fact buses and resistors/R networks are very hard to place and it will consume a lot of contant refresh process. \\ |
| \\ | \\ | ||
| After a look on the different brands and models of LED driver IC **[[http://www.ti.com/product/TLC5958|Texas Instruments TLC5958]]** appeared as a good compromise to drive a lot of RGB LEDs without overloading the core. Designed to be a LED Display driver, its original purpose and features would allow large-sized RGB-LED-based display setups\\ | After a look on the different brands and models of LED driver IC **[[http://www.ti.com/product/TLC5958|Texas Instruments TLC5958]]** appeared as a good compromise to drive a lot of RGB LEDs without overloading the core. Designed to be a LED Display driver, its original purpose and features would allow large-sized RGB-LED-based display setups\\ | ||
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| ==== Data Transfer ==== | ==== Data Transfer ==== | ||
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| - | A serialized design has been chosen to provide data to TLC. Prototype feature only 2 steps but the CORE works like there's 4 modules of 16 steps connected. In order to benchmark reactivity and Transfer time, Core send data for 4 modules. Through an emulated software SPI bus, for this 64 rings Data Sending __takes less than 5ms__ . Different colors and patterns like relative value(-64/63), keyboard(B&W keys) etc... were tested.\\ | + | A serialized design has been chosen to provide data to TLC. Prototype feature only 2 steps but the CORE works like there's 4 modules of 16 steps connected. In order to benchmark reactivity and Transfer time, Core send data for 4 modules(4*16*32*3*16bit=12KBytes). Through an emulated software SPI bus, for this 64 rings Data Sending __takes less than 5ms__ . Different colors and patterns like relative value(-64/63), keyboard(B&W keys) etc... were tested.\\ |
| {{antichambre:img_3658.jpg?300|}}{{:antichambre:img_3657.jpg?300|}}{{antichambre:img_3656.jpg?300|}}\\ | {{antichambre:img_3658.jpg?300|}}{{:antichambre:img_3657.jpg?300|}}{{antichambre:img_3656.jpg?300|}}\\ | ||
| {{antichambre:large.img_3754.jpg?300|}} {{:antichambre:large.3653bd.jpeg?460|}}\\ | {{antichambre:large.img_3754.jpg?300|}} {{:antichambre:large.3653bd.jpeg?460|}}\\ | ||
| - | |||
| ==== GrayScale Clock ==== | ==== GrayScale Clock ==== | ||
| Line 126: | Line 126: | ||
| {{:antichambre:slva645_5_2.png?800|}}\\ | {{:antichambre:slva645_5_2.png?800|}}\\ | ||
| - | TLC is wired like on an SPI bus to Core Board. Here are equivalences:\\ | + | TLC is wired like on an SPI bus to Core Board. Here are connections equivalences:\\ |
| * SCLK => SC | * SCLK => SC | ||
| * DATA => SO | * DATA => SO | ||
| * LAT => RC | * LAT => RC | ||
| * FLAGS READ => SI | * FLAGS READ => SI | ||
| + | **[[stm32f4_module#inputs_outputs_ports|STM32F4 I/O Ports]]** | ||
| + | \\ | ||
| + | \\ | ||
| //Note: Command is coded by putting LAT active during a defined number of SCLK periods.For example for a VSYNC command, LAT must be high during 3 SCLK pulses.//\\ | //Note: Command is coded by putting LAT active during a defined number of SCLK periods.For example for a VSYNC command, LAT must be high during 3 SCLK pulses.//\\ | ||
| Line 152: | Line 154: | ||
| CORE provides a regular Clock with PWM @2MHz .The 12bit counter U16 counts until 257 and trigs U1 wich is a monostable, U1 switchs, resets the counter and stops the clock counter input by U17(D-Flipflop). \\ | CORE provides a regular Clock with PWM @2MHz .The 12bit counter U16 counts until 257 and trigs U1 wich is a monostable, U1 switchs, resets the counter and stops the clock counter input by U17(D-Flipflop). \\ | ||
| \\ | \\ | ||
| - | After a certain time given by the RC couple on U1, U1 switch back and restarts the counter. | + | After a certain time given by the RC couple on U1, U1 switchs back and restarts the counter. |
| By this way we are sure to count the exact 257 Clocks needed and the interval between 2 segments is fixed by the trimpot U19.\\ | By this way we are sure to count the exact 257 Clocks needed and the interval between 2 segments is fixed by the trimpot U19.\\ | ||
| \\ | \\ | ||
| Line 159: | Line 161: | ||
| === Multiplexing Schematic === | === Multiplexing Schematic === | ||
| - | {{:antichambre:tlc_gsclk_topb.png?800|}}\\ | + | {{:antichambre:tlc_gsclk_topb.png?500|}}\\ |
| ADDR_x, ADDR_CLK, GSCLK are connected to the top board...\\ | ADDR_x, ADDR_CLK, GSCLK are connected to the top board...\\ | ||
mb_olre16.txt · Last modified: 2019/04/21 08:50 by antichambre
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