mb_olre16
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| mb_olre16 [2016/09/24 16:37] – [Core-External Driving Concept : TLC5958] antichambre | mb_olre16 [2019/04/21 08:50] (current) – [GrayScale Clock] antichambre | ||
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| In theory it's possible to drive such a SRIO setup but in fact buses and resistors/R networks are very hard to place and it will consume a lot of contant refresh process. \\ | In theory it's possible to drive such a SRIO setup but in fact buses and resistors/R networks are very hard to place and it will consume a lot of contant refresh process. \\ | ||
| - | \\r | + | \\ |
| After a look on the different brands and models of LED driver IC **[[http:// | After a look on the different brands and models of LED driver IC **[[http:// | ||
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| **Frame update is needed only when a change occurs, TLC keep all the frame in memory and continue to distribute it to the 32 addresses lines and 16 rgb leds by address ** | **Frame update is needed only when a change occurs, TLC keep all the frame in memory and continue to distribute it to the 32 addresses lines and 16 rgb leds by address ** | ||
| \\ | \\ | ||
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| ==== GrayScale Clock ==== | ==== GrayScale Clock ==== | ||
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| The TLC needs a GrayScale Clock(GSCLK) and additional control to multiplex 32 addresses (named COMSELx in diagram). The GSCLK signal should be 257 pulses + 1.5~2.5µs of interval between segments . COMSEL management needs 32 multiplexing adress lines for (5 bits coded and decoded directly on the top board).\\ | The TLC needs a GrayScale Clock(GSCLK) and additional control to multiplex 32 addresses (named COMSELx in diagram). The GSCLK signal should be 257 pulses + 1.5~2.5µs of interval between segments . COMSEL management needs 32 multiplexing adress lines for (5 bits coded and decoded directly on the top board).\\ | ||
| - | === Clock Schematic === | + | === Clock Schematic |
| + | \\ | ||
| + | <wrap center round important 60%> | ||
| + | //Note: This circuit is replaced by a simulated one, on a CPLD.// | ||
| + | </ | ||
| {{: | {{: | ||
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| CORE provides a regular Clock with PWM @2MHz .The 12bit counter U16 counts until 257 and trigs U1 wich is a monostable, U1 switchs, resets the counter and stops the clock counter input by U17(D-Flipflop). \\ | CORE provides a regular Clock with PWM @2MHz .The 12bit counter U16 counts until 257 and trigs U1 wich is a monostable, U1 switchs, resets the counter and stops the clock counter input by U17(D-Flipflop). \\ | ||
| \\ | \\ | ||
| - | After a certain time given by the RC couple on U1, U1 switch | + | After a certain time given by the RC couple on U1, U1 switchs |
| By this way we are sure to count the exact 257 Clocks needed and the interval between 2 segments is fixed by the trimpot U19.\\ | By this way we are sure to count the exact 257 Clocks needed and the interval between 2 segments is fixed by the trimpot U19.\\ | ||
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| ADDR_CLK is the multiplexed lines clock . It's used to gate the PWM signal and obtain the GSCLK and of course, as a clock for the ADDR Counter U5. The counter U5 provides the coded ADDR_x lines and an EOF(End Of Frame) when 32 is reached.\\ | ADDR_CLK is the multiplexed lines clock . It's used to gate the PWM signal and obtain the GSCLK and of course, as a clock for the ADDR Counter U5. The counter U5 provides the coded ADDR_x lines and an EOF(End Of Frame) when 32 is reached.\\ | ||
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| + | === Clock version 2 === | ||
| + | |||
| + | <wrap center round todo 60%> | ||
| + | CPLD/FPGA version | ||
| + | </ | ||
mb_olre16.1474735079.txt.gz · Last modified: 2016/09/24 16:37 by antichambre