32 SPI-driven displays

The concept is to buffer the time-critical clock signal. A wire connected directly to the MCU is loaded by the long distance (resistance in the connectors and wires) and could be susceptible to noise. Using a 541 buffer and shunt resistors controls this impedance. The serial data and data/command (DC) signals are also buffered to avoid time propagation errors.

The second purpose is to use a chain of shift registers to provide chip select (CS) signals. It is functionally equivalent to a DOUT module, but the header is directly compatible with GPIO on the Core.

v1.0: first release. Erratum: there is a significant error in that J15 is mirrored. The simplest way to get it working is to swap pairs of the ribbon wires as shown:

Here the header notches are aligned with the silkscreen. Only the first six wires are required.

All parts are THT, start with resistors and caps, IC sockets then headers.

J10B connects to J10B. J15A to J15A. Note the mirrored connection on v1.0

J15A1/J10B1 chain another Display Driver. Note that the J15 connection should not be mirrored for subsequent boards.

The PCB is 100*100mm with 3.2mm diameter holes centred 3.5mm from the edges.

Currently the design is © 2018 antilog devices with all rights reserved; all documentation is CC BY-NC-SA 3.0.